The Field of the Invention
The present invention involves etching processes in microelectronics technology. More particularly, the present invention involves methods of ameliorating etch rate uniformity problems in batch fabrication operations by providing a buffer layer to be etched on each semiconductor substrate in the batch. The present invention also ameliorates destructive etching into otherwise etch-selective structures on a semiconductor substrate due to unwanted prolonged etching into neighboring structures. In particular, the present invention involves use of an electrically conductive buffer layer on a semiconductor substrate that etches faster than other layers and surfaces incident to forming a cavity.
The Relevant Technology
In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above. A semiconductor device refers to a semiconductor substrate upon which at least one microelectronic device has been or is being batch fabricated. A buffer layer in etch processing is a layer of a material to which a specific etch is selective.
Uniformity across a semiconductor device is a concern to the process engineer during many process steps in the fabrication of microelectronic devices. One such process step is formation of cavities by etching in which an etch may leave some cavities incompletely etched and others overetched such that an underlying layer is not exposed or is damaged, respectively.
The problem of etch uniformity can be ameliorated by performing a planarization step before the etch. If a planarization step is not done, and the layer to be etched is uneven, an etch may penetrate the layer and contact the substrate in some places where the layer was over the substrate, and the etch may not contact the substrate in some places where the layer was thick. Such an etch uniformity problem is illustrated in FIG. 1. In FIG. 1, which is a cross-sectional area, the exposing of a fragment of a semiconductor device 10 is illustrated wherein a substrate 12 has four gate stacks 14 built thereupon. Gate stacks 14 comprise a gate oxide layer (not shown), a polysilicon layer 16, a silicide layer 18, and an insulative nitride cap 20. Insulative nitride spacers 22 protect gate stacks 14. An insulative layer 26 covers gate stacks 14 and substrate 12.
FIG. 1 illustrates one example of etch an uniformity problem in which the plane of an insulative layer upper surface 28 is not parallel to the plane of a substrate upper surface 30. An etch of insulative layer 26 will lead to inconsistent etch depths. An etch cavity 32 fails to penetrate and thus fails to provide a completed cavity. An etch cavity 34 overexposes an active area or interconnect lower level and thus damages the underlying layer. In the case of FIG. 1, the underlying layer is substrate 12.
Another problem of etch uniformity is an inadequately executed etch-selective process in which, although selective to structures that are to remain, a prolonged etch will nonetheless damage structures as illustrated in FIG. 2. In FIG. 2, even if the topography of insulative layer 26 is planar, prominent structures on substrate 12, such as gate stacks 14, will be exposed to etching effects and detrimentally etched before substrate 12 is exposed.
What is needed is a method of etching a cavity that avoids the etch uniformity problems of the prior art.